Field of the Invention
The present invention relates to a method of producing a semiconductor device having a contact hole between different electroconductive layers, and more specifically relates to a method of filling the contact hole with an interposed layer to achieve reduction of contact resistance.
Brief description is firstly given for the conventional method of producing a semiconductor device with reference to FIGS. 2(a)-2(c). In the step of FIG. 2(a), an N type impurity diffusion layer 12 is formed in a silicon substrate 11. In the step of FIG. 2(b), a contact hole 14 is formed in an insulating film 13 disposed over the substrate 11. Thereafter, the step of FIG. 2(c) is carried out to form a lead pattern layer 15 composed of aluminum, silicide or high-melting-temperature metal.
In the conventional semiconductor device of sub-micron scale, depth of the impurity diffusion layer 12 shown in FIG. 2(a) is controlled less than 0.4 .mu.m, thereby causing a defect called an alloy spike under the lead pattern 15 made of aluminum in the contact hole 14, which tends to reduce the junction breakdown voltage of the impurity diffusion layer 12. Further, in case that the lead pattern layer 15 is made of silicide or high-melting-temperature metal, the impurity concentration is decreased at the junction of impurity diffusion layer 12 of silicon in the contact hole 14, thereby increasing contact resistance between the lead pattern layer 15 and the impurity diffusion layer 12.
FIG. 10 is a sectional view showing one example of the conventional contact structure between a low resistivity region and a metal lead electrode in an insulating gate field effect transistor. A P.sup.+ type drain or source region 101 is formed in a semiconductor substrate 106 by ion implantation. A contact hole is formed in a field insulating film 103. Thereafter, a metal electrode 104 composed, for example, of aluminum is formed to define a drain electrode or source electrode.
In the above described prior art construction, impurity diffusion is carried out by ion implantation to form P.sup.+ type region. As shown in FIG. 11, in the impurity diffusion by the ion implantation, the activated carrier density is decreased on the surface of the substrate, thereby causing increase in the contact resistance with respect to the metal electrode. In addition, damage may be disadvantageously caused on the substrate surface layer due to the ion implantation. Further, aspect ratio of a step portion in a contact hole may be increased when an opening area of the contact hole is reduced for more efficient integration of transistor circuits, thereby causing opening of the metal lead pattern layer and causing defects due to electromigration at a contact hole edge and due to stress-migration.